`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/11/23 20:23:20
// Design Name: 
// Module Name: rx_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module rx_tb(

    );

    reg clk;
    reg rstn;
    reg uart_rx_in;
    wire[2:0] Baudrate_Set;//波特率输�?
    wire[7:0] uart_rx_Data;
    wire Rx_Done;
    assign Baudrate_Set = 3'd4;
    initial begin
        clk = 0;
    end
    always #10 clk = ~clk;
    initial begin
        
        rstn = 0;
        uart_rx_in = 1;
        #201;
        rstn = 1;
        #200;
        uart_tx_byte(8'h5a);//task.name(port value)
        #9000;

        uart_tx_byte(8'ha5);//task.name(port value)
       // @(posedge Rx_Done);
        #9000;

        uart_tx_byte(8'h86);//task.name(port value)
       // @(posedge Rx_Done);
        #9000;

        uart_tx_byte(8'h68);//task.name(port value)
        //@(posedge Rx_Done);
        #9000;    
        $stop;            
    end
    uart_rx u_uart_rx(
        .clk          ( clk          ),
        .rstn         ( rstn         ),
        .uart_rx_in   ( uart_rx_in   ),
        .Baudrate_Set ( Baudrate_Set ),
        .uart_rx_Data ( uart_rx_Data ),
        .Rx_Done     ( Rx_Done     )
    );


//creat a task
    task uart_tx_byte ;//发送数据任务 =-------= task <task.name>
        input  [7:0] tx_data;
        begin
            uart_rx_in = 1;
            #20;
            uart_rx_in = 0;
            #8680;//保持1位的时间
            //发送数据
            uart_rx_in = tx_data[0] ;
            #8680;
            uart_rx_in = tx_data[1] ;
            #8680 ;
            uart_rx_in = tx_data[2] ;
            #8680 ;
            uart_rx_in = tx_data[3] ;
            #8680 ;
            uart_rx_in = tx_data[4] ;
            #8680 ;
            uart_rx_in = tx_data[5] ;
            #8680 ;
            uart_rx_in = tx_data[6] ;
            #8680 ;
            uart_rx_in = tx_data[7] ;
            #8680 ;
            uart_rx_in = 1 ;
            #8680;
        end
    endtask
endmodule
